1. Field
Exemplary embodiments of the present invention relate to a memory and a memory system including the same.
2. Description of the Related Art
A memory cell of a memory includes a transistor serving as a switch and a capacitor storing a charge, which is data. Data is identified as logic high corresponding to logic ‘1’ or logic low corresponding to logic ‘0’ depending on charge accumulation in a capacitor of a memory cell—in other words, whether the terminal voltage level of the capacitor is high or low.
Theoretically, there is no data loss in the memory cell because the data is stored by way of charge accumulation in the capacitor. However, because of current leakage in the PN junction of the MOS transistor as well as other places, the initial charge accumulated in the capacitor may decrease, and consequently the data stored in the memory cell may be lost. To prevent data loss, the data stored in the memory cell is read and the charge has to be recharged according to the read data periodically before losing the stored data, which is called a refresh operation. The refresh operation allows the memory to keep the stored data without data loss.
FIG. 1 is a circuit diagram illustrating a portion of a cell array included in a memory. In FIG. 1, BL represents a bit line.
Referring to FIG. 1, three word lines WLK−1, WLK, and WLK+1 in the cell array are arranged in parallel. Furthermore, the K-th word line WLK with notation “HIGH_ACT” is an activated word line. The (K−1)th and (K+1)th word lines WLK−1 and WLK+1 are adjacent to the active K-th word line WLK. Furthermore, (K−1)th, K-th and (K+1)th memory cells CELL_K−1 CELL_K, and CELL_K+1 are electrically coupled to the (K−1)th, K-th and (K+1)th word lines WLK−1, WLK, and WLK+1, respectively. The (K−1)th, K-th and (K+1)th memory cells CELL_K−1 CELL_K and CELL_K +1 include (K−1)th, K-th and (K+1)th cell transistors TR_K−1, TR_K, and TR_K+1; and (K−1)th, K-th, and (K+1)th cell capacitors CAP_K−1, CAP_K and CAP_K+1, respectively.
When the K-th word line WLK is activated, the voltages of the adjacent (K−1)th and (K+1)th word lines WLK−1 and WLK+1 fluctuate from coupling between the K-th word line WLK and the adjacent (K−1)th and (K+1)th word lines WLK−1 and WLK+1, thereby influencing charges stored in the (K−1)th and (K+1)th cell capacitors CAP_K−1 and CAP_K+1, which is referred to as word line disturbance. In other words, the probability of data loss of the memory cells CELL_K−1 and CELL_K+1 of the adjacent word lines WLK−1 and WLK+1 increases, which becomes more severe as the activity of the active word line WLK becomes greater.